This application is a continuation of U.S. patent application Ser. No. 13/970,817 filed Aug. 20, 2013, which is hereby incorporated by reference in its entirety.
The present invention relates to data storage adapters, and more specifically, to the hardware implementation of write caches in data storage adapters.
Storage adapters and storage subsystems often include a write cache to improve performance. The write cache may typically be implemented using a relatively fast non-volatile memory (e.g., using a Flash-backed DRAM). Write caches may be used to mitigate performance penalties on write operations, such as the intensive parity calculations required in certain configurations of redundant arrays of independent disks (“RAID”), such as RAID 5 and RAID 6. A write cache can also improve storage performance by consolidating multiple host operations placed in the write cache into a single destage operation, which may be processed more economically by the RAID layer and the disk devices.
The effective size of write caches has grown dramatically over time, due to both an increase in the size of memory chips as well as through the use of compression techniques to compress the data contents of the write cache. At the same time, faster storage devices such as Solid-State Drives (SSDs) have become increasingly popular, which increases the overall throughput required of the storage adapter, and correspondingly increases the computational demands to keep up with the attached drives.